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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xr28v384 3.3v quad lpc uart with 128-byte fifo november 2013 rev. 1.0.0 general description the xr28v384 (v384) is a quad universal asynchronous receiver and transmitter (uart) for the intel low pin count (lpc) bus interface. this device can replace or supplement a super i/o device to add additional serial ports to the system. the v384 uarts support any 16-bit i/o address supported by the system. the register set is based on the industry standard 16550 uart, so the v384 operates with the standard serial port drivers with out requiring a custom driver to be installed. the 128 byte transmit and receive fifos reduce cpu overhead and minimize the chance of buffer overflow and data loss. in addition to the 16550 uart registers, there are also configuration regist er set where enhanced features such as the 9-bit (multidrop) mode, irda mode and the watchdog timer can be enabled. the v384 is available in a 48-pin tqfp package. applications x industrial and embedded pcs x factory automation and process controls x network routers x system board designs features x 128 byte transmit and receive fifo x compliant to lpc 1.1 specifications x -40c to +85c industrial temp operation x watchdog timer with wdtout# signal x 4 independent uart channels programmable i/o mapped base addresses data rates up to 3 mbps selectable rx fifo interrupt trigger levels auto rs-485 half-duplex control mode programmable character lengths (5, 6, 7, 8) with even, odd, or no parity irda mode and separate irtxa# and irrxa# pins for the first uart channel 9-bit (multidrop) mode x external 24mhz/48mhz clock x single 3.3v supply voltage ( 10% ) x 5v tolerant inputs x 48-tqfp package (7mm x 7mm) f igure 1. xr28v384 b lock d iagram l p c b u s in te r fa c e t x f if o ( ir d a e n c o d e r ) m o d e m io s c lo c k d iv id e r r x f if o ( i r d a d e c o d e r ) r t s a # /p s _ c o n f _ 2 e /r s 4 8 5 d t r a # /p s _ 3 e 0 _ ir q a c t s a # , d s r a # , c d a # , r ia # u a r t c h a n n e l a b a u d r a te g e n e r a to r s ta tu s a n d c o n tr o l r e g is te r s v c c g n d w d t o u t # c l k i n p c ir s t # l c l k l f r a m e # l a d [3 :0 ] s e r ir q g lo b a l c o n fig u r a tio n r e g is te r s w a tc h d o g t im e r t x a /p s _ 3 f 8 _ ir q a ir t x a # r x a ir r x a # t x f if o m o d e m io s r x f if o u a r t c h a n n e l b r t s b # /p s _ c o n f _ k e y 1 /r s 4 8 5 d t r b # /p s _ 2 e 0 _ ir q b c t s b # , d s r b # , c d b # , r ib # t x b /p s _ 2 f 8 _ ir q b r x b t x f if o m o d e m io s r x f if o u a r t c h a n n e l c r t s c # /p s _ c o n f _ k e y 0 /r s 4 8 5 d t r c # /p s _ w d t c t s c # , d s r c # , c d c # , r ic # t x c /p s _ 3 e 8 _ ir q c r x c t x f if o m o d e m io s r x f if o u a r t c h a n n e l d r t s d # /r s 4 8 5 d t r d # c t s d # , d s r d # , c d d # , r id # t x d /p s _ 2 e 8 _ ir q d r x d b a u d r a te g e n e r a to r s ta tu s a n d c o n tr o l r e g is te r s b a u d r a te g e n e r a to r s ta tu s a n d c o n tr o l r e g is te r s b a u d r a te g e n e r a to r s ta tu s a n d c o n tr o l r e g is te r s 3 . 3 v 1 0 %
xr28v384 2 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo n ote : tr = tape and reel, f = green / rohs f igure 2. p in o ut a ssignment ordering information p art n umber p ackage o perating t emperature r ange d evice s tatus xr28v384im48-f 48-lead tqfp -40c to +85c active xr28v384im48tr-f 48-lead tqfp -40c to +85c active x r 28v 384 48-tq fp w d to u t# g n d la d 3 la d 2 la d 1 la d 0 lc lk lfr a m e# s e r ir q v c c p c ir s t# c lk in 3 26 9 8 57 10 14 12 11 13 14 15 16 17 18 19 20 21 22 23 24 27 25 26 36 28 29 30 31 32 33 34 35 48 47 46 45 44 43 42 41 40 39 38 37 rtsa#/ps_conf_2e/rs485 r ts b #/p s_c o n f _k e y1/r s485 r x b d tr b #/p s_2e 0_ir q b d s r b# c ts b # v c c g n d r ic # c d c # tx c /p s_3e 8_ir q c tx b /p s_2f8_ir q b r x c irtxa# cdb# rib# ctsa# dsra# dtra#/ps_3e0_irqa rxa txa/ps_3f8_irqa cda# ria# irrxa# dtrc#/ps_wdt rtsc#/ps_conf_key0/rs485 dsrc# rid# cdd# txd/ps_2e8_irqd rxd dtrd# rtsd#/rs485 dsrd# ctsd# ctsc#
xr28v384 3 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo pin descriptions pin description n ame 48-tqfp pin# t ype d escription lpc bus interface pcirst# 1 i active low reset signal. lad3 lad2 lad1 lad0 45 6 7 i/o multiplexed address / data bus [3:0]. see ?section 1.2, lpc bus interface? . lclk 8 i lpc clock input up to 33.3mhz. lframe# 9 i active low lpc frame signal indicates start of a ne w cycle or termination of a broken cycle. serirq 10 i/o bi-directional pin for sending interrupts. by defau lt this pin is tri-stated when idle. interrupts can be active high or low. see ?section 1.2.1, serial irq? and see ?section 2.2.1.3, interrupt enable register (ier) - read/write? for more infor- mation regarding interrupts . uart i/o interface ctsd# 13 i uart channel d clear-to-send (active low) or genera l purpose input. this input should be connected to vcc or gnd when not used. dsrd# 14 i uart channel d data-set-ready (active low) or gener al purpose input. this input should be connected to vcc or gnd when not us ed. rtsd#/rs485 15 o uart channel d request-to-send (active low) or gene ral purpose output or automatic rs485 half duplex control pin. see ?section 1.4.4, auto rs-485 half-duplex control? . dtrd# 16 o uart channel d data-terminal-ready (active low) or general purpose output. rxd 17 i uart channel d receive data. normal receive data in put must idle at logic 1 condition. this input should be connected to vcc or gnd when not used. txd / ps_2e8_irqd 18 o uart channel d transmit data. the txd signal will b e a logic 1 during reset or idle (no data). if it is not used, leave it unconne cted. this pin has an internal pull-up resistor and is sam pled upon power-up or reset. this will determine the default register settings fo r uart channel d. the regis- ters can later be modified by the software. see table 1 ?uart power on con- figuration? . cdd# 19 i uart channel d carrier-detect (active low) or gener al purpose input. this input should be connected to vcc or gnd when not used. rid# 20 i uart channel d ring-indicator (active low) or gener al purpose input. this input should be connected to vcc or gnd when not used. ctsc# 21 i uart channel c clear-to-send (active low) or genera l purpose input. this input should be connected to vcc or gnd when not used. dsrc# 22 i uart channel c data-set-ready (active low) or gener al purpose input. this input should be connected to vcc or gnd when not us ed.
xr28v384 4 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo rtsc# / ps_conf_key0/ rs485 23 o uart channel c request-to-send (active low) or gene ral purpose output or automatic rs485 half-duplex control pin. see ?section 1.4.4, auto rs-485 half-duplex control? . this pin has an internal pull-up resistor and is sam pled upon power-up or reset. see table 1 ?uart power on configuration? . dtrc# / ps_wdt 24 o uart channel c data-terminal-ready (active low) or general purpose output. this pin has an internal pull-up resistor and is sam pled upon power-up or reset. the registers can later be modified by the software. see table 1 ?uart power on configuration? . rxc 25 i uart channel c receive data. normal receive data in put must idle at logic 1 condition. this input should be connected to vcc or gnd when not used. txc / ps_3e8_irqc 26 o uart channel c transmit data. the txc signal will b e a logic 1 during reset or idle (no data). if it is not used, leave it unconne cted. this pin has an internal pull-up resistor and is sam pled upon power-up or reset. this will determine the default register settings fo r uart channel c. the regis- ters can later be modified by the software. see table 1 ?uart power on con- figuration? . cdc# 27 i uart channel c carrier-detect (active low) or gener al purpose input. this input should be connected to vcc or gnd when not used. ric# 28 i uart channel c ring-indicator (active low) or gener al purpose input. this input should be connected to vcc or gnd when not used. ctsb# 31 i uart channel b clear-to-send (active low) or genera l purpose input. this input should be connected to vcc or gnd when not used. dsrb# 32 i uart channel b data-set-ready (active low) or gener al purpose input. this input should be connected to vcc or gnd when not us ed. rtsb# / ps_conf_key1/ rs485 33 o uart channel b request-to-send (active low) or gene ral purpose output or aut- matic rs485 half-duplex control pin. see ?section 1.4.4, auto rs-485 half- duplex control? . this pin has an internal pull-up resistor and is sam pled upon power-up or reset see table 1 ?uart power on configuration? . dtrb# / ps_2e0_irqb 34 o uart channel b data-terminal-ready (active low) or general purpose output. this pin has an internal pull-up resistor and is sam pled upon power-up or reset. this will determine the default register settings fo r uart channel b. the regis- ters can later be modified by the software. see table 1 ?uart power on con- figuration? . rxb 35 i uart channel b receive data. normal receive data inp ut must idle at logic 1 condition. this input should be connected to vcc or gnd when not used. txb / ps_2f8_irqb 36 o uart channel b transmit data. the txb signal will b e a logic 1 during reset or idle (no data). if it is not used, leave it unconne cted. this pin has an internal pull-up resistor and is sam pled upon power-up or reset. this will determine the default register settings fo r uart channel b. the regis- ters can later be modified by the software. see table 1 ?uart power on con- figuration? . cdb# 37 i uart channel b carrier-detect (active low) or gener al purpose input. this input should be connected to vcc or gnd when not used. pin description n ame 48-tqfp pin# t ype d escription
xr28v384 5 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo pin type: i=input, o=output, i/o= input/output, pw r=power supply. rib# 38 i uart channel b ring-indicator (active low) or genera l purpose input. this input should be connected to vcc or gnd when not used. ctsa# 39 i uart channel a clear-to-send (active low) or general purpose input. this input should be connected to vcc or gnd when not used. dsra# 40 i uart channel a data-set-ready (active low) or gener al purpose input. this input should be connected to vcc or gnd when not us ed. rtsa# / ps_conf_2e/ rs485 41 o uart channel a request-to-send (active low) or gene ral purpose output. this pin has an internal pull-up resistor and is sam pled upon power-up or reset. the registers can later be modified by the software. see table 1 ?uart power on configuration? . dtra# / ps_3e0_irqa 42 o uart channel a data-terminal-ready (active low) or general purpose output. this pin has an internal pull-up resistor and is sam pled upon power-up or reset. this will determine the default register settings fo r uart channel a. the regis- ters can later be modified by the software. see table 1 ?uart power on con- figuration? . rxa 43 i uart channel a receive data.the receive data input must idle at logic 1 condi- tion. this input should be connected to vcc or gnd when not used. txa / ps_3f8_irqa 44 o uart channel a transmit data. the txa signal will be a logic 1 during reset or idle (no data). if it is not used, leave it unconne cted. this pin has an internal pull-up resistor and is sam pled upon power-up or reset. this will determine the default register settings fo r uart channel a. the regis- ters can later be modified by the software. see table 1 ?uart power on con- figuration? . cda# 45 i uart channel a carrier-detect (active low) or gener al purpose input. this input should be connected to vcc or gnd when not used. ria# 46 i uart channel a ring-indicator (active low) or genera l purpose input. this input should be connected to vcc or gnd when not used. irrxa# 47 i infrared receiver input. the infrared receive data i nput idles at logic 0. this input should be connected to gnd when not used. irtxa# 48 o infrared transmitter output. the irtxa# signal will be a logic 0 during reset or idle (no data). ancillary signals clkin 12 i clock input 24 mhz or 48 mhz. wdtout# 2 o active low watchdog timer output. this pin is open drain and needs a pull-up resistor if it is used. the registers can later be m odified by the software. see table 1 ?uart power on configuration? . power signals vcc 11, 30 pwr 3.3v 10% power supply. gnd 3, 29 pwr power supply common, ground. pin description n ame 48-tqfp pin# t ype d escription
xr28v384 6 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo 1.0 functional descriptions 1.1 power on strapping options at power-on, strapping options for each pin listed in table 1 result in the register values based upon the pin state selected. these register values can also be m odified by the software. 1.1.1 uart/watchdog timer options the v384 provides seven pins for power on hardware strapping options to select the settings of the uar t channels and watchdog timer. after power-on, the enable, base address high & low , irqsel registers can be modified by the software. 1.1.2 configuration port and key selection options 1.1.2.1 configuration port selection option the configuration registers are programmed by the i ndex port and the data port. the port address is determined by the strap pin rtsa#/ps_conf_2e/rs485. if an external pull-down resistor is not installed , the t able 1: uart p ower o n c onfiguration p in n umber p in n ame p in s tate r egister v alues c omment e nable (0 x 30) b ase a ddress h igh r egister (0 x 60) b ase a ddress l ow r egister (0 x 61) irqsel (0 x 70) 18 txd / ps_2e8_irqd 1 0x1 0x2 0xe8 0x9 0 0x0 0x0 0x0 0x0 26 txc / ps_3e8_irqc 1 0x1 0x3 0xe8 0x5 0 0x0 0x0 0x0 0x0 34 dtrb# / ps_2e0_irqb 1 0x1 0x2 0xe0 0x4 when both pins are high, the base address will be 0x2f8. 0 0x0 0x0 0x0 0x0 36 txb / ps_2f8_irqb 1 0x1 0x2 0xf8 0x4 0 0x0 0x0 0x0 0x0 42 dtra# / ps_3e0_irqa 1 0x1 0x3 0xe0 0x3 when both pins are high, the base address will be 0x3f8. 0 0x0 0x0 0x0 0x0 44 txa / ps_3f8_irqa 1 0x1 0x3 0xf8 0x3 0 0x0 0x0 0x0 0x0 24 dtrc# / ps_wdt 1 0x1 0x4 0x42 0x0 0 0x0 0x0 0x0 0x0
xr28v384 7 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo default value of the rtsa#/ps_conf_2e/rs485 pin is ?1? when the system powers on. therefore, the defau lt index port address is 0x2e and the data port addres s is 0x2f. 1.1.2.2 configuration entry key options in order to enable the configuration register acces s mode, the entry key needs to be written consecuti vely twice to the index port. the entry key is generated by the power on setting pins rtsb#/ps_conf_key1/ rs485 and rtsc#/ps_conf_key0/rs485. in order to disable the configuration register acce ss mode, 0xaa must be written to the index port. 1.1.2.3 example 1.1.2.3.1 index port address 0x2e & data port addres s 0x2f (default) write (0x2e, 0x67); write (0x2e, 0x67); //write entry key (0x67) twice to configuration port //enable access to the configuration registers write (0x2e, 0x20); //select the dev_id_m register read (0x2f); //read the dev_id_m register write (0x2e, 0x21); //select the dev_id_l register read (0x2f); //read the dev_id_l register write (0x2e, 0x25); //select the clock select register write (0x2f, 0x1); //select the input clock frequency 48 mhz write (0x2e, 0x7); //select the ldn register write (0x2f, 0x1); //select the uart channel b write (0x2e, 0xf6); //select the fifo mode select re gister of uart channel b write (0x2f, 0x3); //set the fifo size 128 bytes, //rx trigger level 1, 4, 8, 14 and no delay for thr empty interrupt write (0x2e, 0x30); write (0x2f, 0x1); //enable the uart channel b write (0x2e, 0xaa); //disable access to configuratio n registers t able 2: c onfiguration p ort s election rtsa#/ps_conf_2e/rs485 (p in 41) i ndex p ort a ddress d ata p ort a ddress 0 0x4e 0x4f 1 (default) 0x2e 0x2f t able 3: c onfiguration e ntry k ey rtsb#/ps_conf_key1/rs485 (p in 33) rtsc#/ps_conf_key0/rs485 (p in 23) e ntry k ey 0 0 0x77 0 1 0xa0 1 0 0x87 1 1 0x67 (default)
xr28v384 8 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo 1.1.2.3.2 index port address 0x4e & data port addres s 0x4f write (0x4e, 0x67); write (0x4e, 0x67); //write entry key (0x67) twice to configuration port //enable access to the configuration registers write (0x4e, 0x23); //select the vid_m register read (0x4f); //read the vid_m register write (0x4e, 0x24); //select the vid_l register read (0x4f); //read the vid_l register write (0x4e, 0x25); //select the clock select register write (0x4f, 0x0); //select the input clock frequency 24 mhz write (0x4e, 0x7); //select the ldn register write (0x4f, 0x0); //select the uart channel a write (0x4e, 0x60); write (0x4f, 0x3); //set the uart channel a base add ress high byte as 0x3 write (0x4e, 0x61); write (0x4f, 0xf8); //set the uart channel a base ad dress low byte as 0xf8 write (0x4e, 0xf6); //select the fifo mode select re gister of uart channel a write (0x4f, 0x0); //set the fifo size 16 bytes, //rx trigger level 1, 4, 8, 14 and no delay for thr empty interrupt write (0x4e, 0x30); write (0x4f, 0x1); //enable the uart channel a write (0x4e, 0xaa); //disable access to the configur ation registers 1.2 lpc bus interface the lpc bus interface has a 4-bit multiplexed addre ss/data bus, 1 reset signal, 1 clock and 1 control signal. it also has one interrupt signal. the v384 implements the following signals of the lpc bus. lframe# is used by the host to start or stop transf ers. lclk is a clock used for synchronization. pcirst# is an active low reset signal. lad[3:0] signal lines communicate device address, c ontrol (read, write, wait and transfer type), and d ata information over the lpc bus between a host and a p eripheral. interrupt requests are issued through serirq. 1.2.1 serial irq the v384 supports a serial irq scheme specified in s pecification for serialized irq support for pci sys tem rev6.0 which allows serirq pin to be shared with mu ltiple devices . the serirq signal is tri-stated when idle. the serirq is divided into 3 types of time sl ots known as frames: start frame, irq frame, and st op frame. the serirq uses lclk for timing. there are t wo modes of operation for serirq signal: quiet mode and continuous mode. these two modes are discussed in further detail in ?section 1.2.1.1, start frame? .
xr28v384 9 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo 1.2.1.1 start frame the start frame indicates begining of the serirq cy cle. during this frame the serirq is driven low for 4-8 clock cycles. it can be initiated by the host or v3 84 depending on the mode of operation. in the continuous mode, only the host controller in itiates the start frame to update the serirq line information. the host controller drives the serirq signal low for 4 to 8 clock periods. upon a reset, the serirq signal defaults to the continuous mode for th e host controller to initiate the first start frame. in the quiet mode, the start frame is initiated by the device/host. the v384 drives the serirq signal active low for one clock to initiate a start frame, and th en tri-states it immediately. the host controller w ill then take over driving serirq signal low in the next clock an d will continue driving the serirq low for 3 to 7 c lock periods. this makes the total number of clocks low for 4 to 8 clock periods. after these clocks, the h ost controller will drive the serirq high for one clock and then tri-states it. a start frame may not be initiated while serirq is active. the serirq is active between start and stop frames while it is idle between stop and start fram es. 1.2.1.2 irq frame once the start frame has been initiated, all the pe ripherals must start counting frames based on the r ising edge of the clock (lclk). each irq frame is three clocks : sample phase, recovery phase, and turn-around phase. during the sample phase, the peripheral driv es serirq low if the corresponding irq is active. i f the corresponding irq is inactive, then serirq will be left tri-stated. during the recovery phase, the per ipheral device drives the serirq high. during the turn-arou nd phase, the peripheral device leaves the serirq tr i- stated. the v384 supports irq3, irq4, irq5, irq7, i rq9, irq10, and irq11. t able 4: serirq s ampling p eriods irq/d ata f rame s ignal s ampled n umber of clocks past s tart 1 irq0 2 2 irq1 5 3 smi# 8 4 irq3 11 5 irq4 14 6 irq5 17 7 irq6 20 8 irq7 23 9 irq8 26 10 irq9 29 11 irq10 32 12 irq11 35 13 irq12 38 14 irq13 41 15 irq14 44 16 irq15 47 17 iochck# 50 18 inta# 53 19 intb# 56 20 intc# 59 21 intd# 62 32:22 unassigned 95
xr28v384 10 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo 1.2.1.3 stop frame after all irq/data frames have been completed, the host controller will terminate serirq by a stop fra me. only the host controller can initiate the stop fram e by driving serirq low for 2 or 3 clocks. if the s top frame is low for 2 clocks, the next serirq cycle will be t he quiet mode whereas if it is low for 3 clocks, the next serirq cycle will be the continuous mode. 1.3 watchdog timer (wdt) the wdt is typically used in a system to initiate a ny of the several types of corrective action, inclu ding processor reset, power cycling, fail-safe activatio n etc. the watchdog timer of v384 is an 8 bit count er controlled by six registers. see ?section 2.1.2.2, watchdog timer registers (ldn = 0x08)? on page 26. wdtout# idles high and will transition low when a t ime out occurs. the v384 provides three time intervals: 10 ms, 1s and 1 minute allowing for time outs ranging from approximately 2.5 seconds to more t han 4 hours. see ?section 2.1.2.2.4, wdt timer status and contro l register - read/write? to set up time interval. 1.4 uart 1.4.1 external clock input (clkin) along with lclk, the v384 also needs an external cl ock for uart data communication. it can support any clock up to 48mhz. the 24mhz and 48mhz are the stan dard clock frequencies supported by the v384. see ?section 2.1.1.5, clock select register - read/writ e? . 1.4.1.1 programmable baud rate generator each uart has its own baud rate generator (brg) wit h a prescaler. the prescaler is controlled by bit[1 :0] of enhanced multifunction register - read/write. table 5 shows the standard data rates available with a 24 m hz external clock at 16x sampling rate and internal clock frequency set to 1.8462 mhz. the div isor value can be calculated for dll/dlm with the f ollowing equation. table 8 lists the different internal clock settings. divisor (decimal) = (internal clock frequency ) / ( serial data rate x 16) t able 5: t ypical data rates with a 1.8462m hz i nternal clock b aud rate ( bps ) d ivisor for 16x clock (decimal) d ivisor for 16x clock (hex) dlm p rogram v alue (hex) dll p rogram v alue (hex) a ctual b aud rate d ata r ate e rror (%) 150 768 300 03 00 150.24 0.2 300 384 180 01 80 300.48 0.2 600 192 c0 00 c0 600.96 0.2 1200 96 60 00 60 1201.92 0.2 2400 48 30 00 30 2403.85 0.2 4800 24 18 00 18 4807.69 0.2 9600 12 0c 00 0c 9615.39 0.2 19200 6 06 00 06 19230.77 0.2 38400 3 03 00 03 38461.54 0.2 57600 2 02 00 02 57692.31 0.2 115200 1 01 00 01 115384.6 0.2
xr28v384 11 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo 1.4.2 transmitter the transmitter section comprises of an 8-bit trans mit shift register (tsr) and up to 128 bytes of fif o which includes a byte-wide transmit holding register (thr ). tsr shifts out every data bit with the internal s ampling clock. the transmitter sends the start bit followed by the number of data bits, inserts the proper pari ty bit if enabled, and adds the stop bit(s). the status of th e thr and tsr are reported in the line status regis ter (lsr bit-5 and bit-6). 1.4.2.1 transmit holding register (thr) - write only the transmit holding register is an 8-bit register providing a data interface to the host processor. th e host writes transmit data byte to the thr to be converted into a serial data stream including start bit, dat a bits, parity bit and stop bit(s). the least significant bit (bit -0) becomes first data bit to go out. the thr is th e input register to the transmit fifo of up to 128 bytes when fifo o peration is enabled by fcr bit-0. every time a writ e operation is made to the thr, the fifo data pointer is automatically bumped to the next sequential dat a location. 1.4.2.2 transmitter operation in non-fifo mode the host loads transmit data to thr one character a t a time. the thr empty flag (lsr bit-5) is set whe n the data byte is transferred to tsr. thr flag can gener ate a transmit empty interrupt (isr bit-1) when it is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr becomes completely empty. f igure 3. t ransmitter o peration in non -fifo m ode transmit holding register (thr) transmit shift register (tsr) data byte l sb m sb thr interrupt (isr bit-1) enabled by ier bit-1 txnofifo1 clock
xr28v384 12 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo 1.4.2.3 transmitter operation in fifo mode the host may fill the transmit fifo with up to 128 bytes of transmit data. the thr empty flag (lsr bit -5) is set whenever the fifo is empty. the thr empty flag can g enerate a transmit empty interrupt (isr bit-1) when the fifo becomes empty. the transmit empty interrupt is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr/fifo becomes empty. 1.4.3 receiver the receiver section contains an 8-bit receive shif t register (rsr) and up to 128 bytes of fifo which includes a byte-wide receive holding register (rhr) . the rsr uses the internal sampling clock for tim ing. it verifies and validates every bit on the incoming ch aracter in the middle of each data bit. on the fall ing edge of a start or false start bit, an internal receiver co unter starts counting at the clock rate. after 8 clo cks the start bit period should be at the center of the start bit. at this time the start bit is sampled and if it is st ill a logic 0 it is validated. evaluating the start bit in this manner prevents the receiver from assembling a false chara cter. the rest of the data bits and stop bits are sampled and v alidated in this same manner to prevent false frami ng. if there were any error(s), they are reported in the l sr register bits 2-4. upon unloading the receive da ta byte from rhr, the receive fifo pointer is bumped and th e error tags are immediately updated to reflect the status of the data byte in rhr register. rhr can generate a receive data ready interrupt upon receiving a char acter or delay until it reaches the fifo trigger level. f urthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4 word lengths as defined by lcr[ 1:0] plus 12 bits time. this is equivalent to 3.7-4.6 character times. the rhr interrupt is enabled by ier bit-0. see figure 5 . f igure 4. t ransmitter o peration in fifo m ode transmit data shift register (tsr) transmit data byte thr interrupt (isr bit-1) when tx fifo becomes empty. fifo is enabled by fcr bit-0=1 transmit fifo clock txfifo1
xr28v384 13 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo 1.4.3.1 receive holding register (rhr) - read-only the receive holding register is an 8-bit register t hat holds a receive data byte from the receive shif t register. it provides the receive data interface to t he host processor. the rhr register is part of the receive fifo of up to 128 bytes by 11-bits wide, the 3 extr a bits are for the 3 error tags to be reported in ls r register. when the fifo is enabled by fcr bit-0, the rhr cont ains the first data character received by the fifo. after the rhr is read, the next character byte is loaded into the rhr and the errors associated with the cur rent data byte are immediately updated in the lsr bits 2-4. f igure 5. r eceiver o peration in non -fifo m ode f igure 6. r eceiver o peration in fifo m ode receive data shift register (rsr) receive data byte and errors rhr interrupt (isr bit-2) receive data holding register (rhr) rxfifo1 clock receive data characters data bit validation error tags in lsr bits 4:2 r eceive d ata s hift r egister (r s r) r xfifo 1 c lock error tags (up to 128-sets) error tags in lsr bits 4:2 r eceive d ata c haracters d ata b it v alidation r eceive d ata fifo r eceive d ata r eceive d ata b yte and e rrors r h r interrupt (is r bit-2) program m ed for desired f if o trigger level. f if o is e nabled by fc r bit-0=1 fifo trigger=8 e xam ple : - r x fifo trigger level selected at 8 bytes u p to 128 byte 11-bit w idth f if o
xr28v384 14 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo 1.4.4 auto rs-485 half-duplex control the auto rs-485 half-duplex control feature changes the behavior of the rts#/rs485 pin when enabled by enhanced multifunction register - read/write bit-4. if enabled, by default, it de-asserts rts#/rs 485 ouput following the last stop bit of the last character t hat has been transmitted. this helps in turning arou nd the transceiver to receive the remote station?s respons e. when the host is ready to transmit data packet, i t only has to load data bytes to the transmit fifo. the transm itter automatically asserts rts#/rs485 output prior to sending the data. the polarity of rts#/rs485 signal can be modified by bit-5 of enhanced multifunction register. 1.4.5 normal multidrop (9-bit) mode normal multidrop mode is enabled when bit-7 of enha nced multifunction register in the uart device configuration registers is set to ?1?. in the multi drop (9-bit) mode, the parity bit becomes the addres s/data bit. if a data byte is received (9th bit is '0'), it wil l be loaded into the rx fifo and the parity error b it will be '0'. if an address byte is received (9th bit is '1'), it will be loaded into the rx fifo and the parity error bit will be '1'. when the address byte has been received, the softwar e will need to examine the byte: if the address matc hes its slave address, the receiver will receive the sub sequent data; if the address does not match its slav e address, then the receiver will discard the data. 1.4.5.1 auto address detection auto address detection mode is enabled when bit-6 o f enhanced multifunction register (0xf0) in uart de vice configuration registers set is set to ?1?. the desi red slave address will need to be written into the 9-bit mode slave address register (0xf4) in the uart device co nfiguration registers set. if the received byte is an address byte that does not match the programmed character i n the 9-bit mode slave address register, the receive r will discard these data. upon receiving an address byte that matches the 9-bit mode slave address register character, the receiver will automatically push th e address byte into the rx fifo and set the parity error bit in the lsr register. the receiver also generates an ls r interrupt if enabled. the receiver will then rece ive the subsequent data. if another address byte is received and does not match the programmed 9-bit mode slave address register value, then the receiver will igno re the data that follows.
xr28v384 15 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo 1.4.6 infrared mode the v384 uart channel a includes the infrared encod er and decoder compatible to irda (infrared data association) version 1.0. the infrared encoder send s out a 3/16 of a bit wide or 1.6 us high pulse for each ?0? bit in the transmit data stream with a data rate up to 115.2 kbps. this signal encoding reduces the on- time of the infrared led, hence reduces the power consumpti on. see figure 7 . the infrared encoder and decoder are enabled by set ting infrared mode control register - read/write bit-4 to a ?1?. the irrxa# input assumes an idle level of logic zero after a reset and power up, see figure 7 . the irrxa# input will assume an idle level of logic hig h if bit-0 of the infrared mode control register - read/ write is set to ?1?. the irtxa# is idle at low by defaul t. the irtxa# will be idle at high if bit-1 of the infrared mode control register - read/write is set to ?1?. typically, the wireless infrared decoder receives t he input pulse from the infrared sensing diode on t he irrxa# pin. each time it senses a light pulse, it returns a logic 0 to the data bit stream. f igure 7. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding character data bits start stop 0 0 0 0 0 1 1 1 1 1 bit time 1/16 clock delay irdecoder-1 rx data receive ir pulse character data bits start stop 0 0 0 0 0 1 1 1 1 1 tx data transmit ir pulse (irtxa# pin) bit time 1/2 bit time 3/16 bit time or 1.6 us irencoder-1 (irrxa# pin)
xr28v384 16 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo 1.4.7 internal loopback the v384 provides an internal loopback capability f or system diagnostic purposes. the internal loopbac k mode is enabled by setting mcr register bit-4 to logic 1 . figure 8 shows how the modem port signals are re- configured. transmit data from the transmit shift r egister output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending. the tx pin is held high or mar k condition while rts# and dtr# are de-asserted, and cts#, dsr# cd# and ri# inputs are ignored. caution: the rx input must be held high during loopback test else upon exiting the loopback test the uart may d etect and report a false ?break? signal. f igure 8. i nternal l oopback t x r x modem / general purpose control logic internal data bus lines and control signals r t s # m c r b it-4 = 1 v c c v c c t ra n s m it s h ift r e g is te r (t h r /f if o ) r e c e iv e s h ift r e g is te r (r h r /f if o ) c t s # d t r # d s r # r i# c d # o p 1 # r t s # c t s # d t r # d s r # r i# c d # v c c o p 2 #
xr28v384 17 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo 1.5 serial transceiver interface the v384 is typically used with rs-232, rs-485 and ir transceivers. the following figure shows typical connections from the uart to the different transcei vers. for more information on rs-232 and rs-485/422 transceivers, go to www.exar.com or send an e-mail to uarttechsupport@exar.com . f igure 9. xr28v384 t ypical s erial i nterface c onnections vcc vcc rs-485 full-duplex serial interface gnd cd # dsr# cts# dtr# rts# rx tx di ro uart rs-485 transceiver full-duplex tx+ tx- rx+ rx- ri # nc nc vcc de re# vcc v c c v c c r s - 2 3 2 f u ll -m o d e m s e r ia l in te r fa c e g n d r i# c d # d s r # c t s # r t s # d t r # r x t x t 1 in r 1 o u t t 2 in t 3 in r 2 o u t r 3 o u t r 4 o u t r 5 o u t g n d u a r t r s -2 3 2 t r a n s c e iv e r
xr28v384 18 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo 1.6 device reset the pcirst# input resets the internal registers and the serial interface outputs to their default state s. the pcirst# assertion for general system reset may occur at any time and may be asynchronous to lclk. f igure 10. xr28v384 t ypical s erial i nterface c onnections vcc vcc rs-485 half-duplex serial interface gnd cd # dsr# cts# dtr# rts# rx tx di ro uart rs-485 transceiver half-duplex y z ab ri # nc vcc de re# vc c v c c in frared c on nection g n d r i# c d # d s r # c t s # r t s # d tr # ir r x 1# ir tx 1# t x d r x d u a r t ir transceiver v c c n c n c
xr28v384 19 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo 2.0 register details the register map of v384 is primarily divided into two sections: x configuration register set x uart internal register set 2.1 configuration register there are two different sets of configuration regis ters: the global control register set and the devic e configuration register set. the global control regis ters can be used to perform software reset, select clock input frequency, configure watchdog timer, configur ation port selection and read vendor id and device id. the device configuration registers configure all 4 uart s to enable the uart channel, base address, irq channel, internal clock frequency, ir control, 9-bi t mode slave address and fifo mode. the watchdog ti mer can also be configured in the device configuration registers set including enable the watchdog timer, configure base address, irq channel, timer count nu mber and monitor the timer status. x global control registers the global control register set is the set of regist ers that are shared among all the devices of v384. table 6 describes the list of all the global control regist ers. t able 6: lpc b us g lobal c ontrol r egisters a ddress [a7:a0] r egister r ead /w rite c omment r eset s tate 0x02 software reset register read/write bits [7:0] = 0 x00 0x07 logic device number register (ldn) read/write bit s [7:0] = 0x00 0x20 device id msb register (dev_id_m) read-only bits [ 7:0] = 0x03 0x21 device id lsb register (dev_id_l) read-only bits [ 7:0] = 0x84 0x23 vendor id msb register (vid_m) read-only bits [7:0 ] = 0x13 0x24 vendor id lsb register (vid_l) read-only bits [7:0 ] = 0xa8 0x25 clock select register (clksel) read/write bits [7: 0] = 0x00 0x26 watchdog timer control register (wdt) read/write bits [7:0] = 0x00 0x27 port select register read/write bits [7:0] = 0x00
xr28v384 20 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo x device configuration registers the device configuration register set is specific t o each device of the v384. the v384 has two types o f devices: 1) uart 2) watchdog timer. it has 4 uart d evices and 1 watchdog timer. all the uarts have similar register set except uarta. uarta has an add itional register to control ir function. the device configuration register set can be access ed through indirect addressing described in ?section 1.1.2.3, example? . table 7 lists the device configuration registers. t able 7: d evice c onfiguration r egisters a ddress [a7:a0] r egister r ead /w rite r eset s tate c omment uarta (ldn=0x00) 0x30 uart enable register (enable) read/write see table 1 ?uart power on configuration? 0x60 base address high register read/write 0x61 base address low register read/write 0x70 irq channel select register read/write 0xf0 enhanced multifunction register read/write 0x00 0xf1 ir control register read/write 0x44 0xf4 9-bit mode slave address register read/write 0x00 0xf5 9-bit mode slave address mask register read/wr ite 0x00 0xf6 fifo mode select register read/write 0x00 uartb (ldn=0x01) uartc (ldn=0x02) uartd (ldn=0x03) 0x30 uart enable register (enable) read/write see table 1 ?uart power on configuration? 0x60 base address high register read/write 0x61 base address low register read/write 0x70 irq channel select register read/write 0xf0 enhanced multifunction register read/write 0x00 0xf4 9-bit mode slave address register read/write 0x00 0xf5 9-bit mode slave address mask register read/wr ite 0x00 0xf6 fifo mode select register read/write 0x00 wdt (ldn=0x08) 0x30 watchdog enable register read/write 0x01 see table 1 ?uart power on configuration? 0x60 base address high register read/write 0x04 0x61 base address low register read/write 0x42 0x70 irq channel select register read/write 0x00 0xf0 timer status and control register read/write 0x02 0xf1 timer count number register read/write 0x0a
xr28v384 21 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo 2.1.1 global control registers 2.1.1.1 software reset register software reset resets the device configuration regis ters to their factory defaults. strapping pins from table 1 are not sampled during a software reset. bit [0]: software reset x logic 0 = disable software reset (default). x logic 1 = enable software reset. after the software reset, this bit will turn to ?0? automatically. bits [7:1]: reserved 2.1.1.2 logic device number register - read/write this register selects device configuration register set among the 4 channel uarts and the watchdog timer. bits [7:0]: select different device configuration r egister set. x 0x00 = select uart a device configuration register (default). x 0x01 = select uart b device configuration register. x 0x02 = select uart c device configuration register. x 0x03 = select uart d device configuration register. x 0x08 = select watchdog timer device configuration r egister. 2.1.1.3 device id msb/lsb register - read only dev_id_m (0x20): this register provides upper byte device id for xr 28v384. the default value is 0x03. dev_id_l (0x21): this register provides lower byte device id for xr2 8v384. the default value is 0x84. 2.1.1.4 vendor id msb/lsb register - read only vid_m (0x23): this register value provides upper byte of exar?s ven dor id. the default value is 0x13. vid_l (0x24): this register value provides lower byte of exar?s ve ndor id. the default value is 0xa8. 2.1.1.5 clock select register - read/write this register selects the clock frequency. bit [0]: clock select x logic 0 = the clkin is 24 mhz (default). x logic 1 = the clkin is 48 mhz. bits [7:1]: reserved 2.1.1.6 watchdog timer control register - read/writ e this register controls the watchdog timer. bit [0]: assert a low pulse from wdtout# pin x logic 0 = watchdog timer (wdt) will assert a low pu lse from wdtout# pin (default). x logic 1 = watchdog timer (wdt) will not assert a lo w pulse from wdtout# pin, but the timeout status wi ll be set. bit [1]: restart timer x logic 0 = read watchdog timer (wdt) will restart th e timer (default). x logic 1 = read watchdog timer (wdt) will not restar t the timer.
xr28v384 22 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo bits [7:2]: reserved 2.1.1.7 port select register - read/write this register selects the configuration port. bits [1:0]: select configuration entry key the default value of these bits are determined by r tsb#/ps_conf_key1/rs485 and rtsc/ ps_conf_key0/rs485. see table 3 ?configuration entry key? . x ?00? = the entry key is 0x77. x ?01? = the entry key is 0xa0. x ?10? = the entry key is 0x87. x ?11? = the entry key is 0x67. bits [3:2]: reserved bit [4]: select configuration port the default value of this bit is determined by rtsa #/ps_conf_2e/rs485 pin. see table 2 ?configuration port selection? . x logic 0 = the configuration port is 0x2e/0x2f. x logic 1 = the configuration port is 0x4e/0x4f. bits [7:5]: reserved 2.1.2 device configuration registers in order to access device configuration register se t, the configuration regsiter access mode has to be enabled. the value in the ldn register determines w hich device?s configuration register set to access. example: if ldn register = 0x02, modifying uart enable regi ster (0x30) will modify uart enable register of channel c. 2.1.2.1 uart registers 2.1.2.1.1 uart enable register (enable) - read/writ e this register enables/disables the uart selected in the ldn register. bit [0]: enable/disable uart the default value of this bit is determined by the strapping options. see table 1 ?uart power on configuration? . this bit can be programmed after power up. x logic 0 = disable the uart selected in ldn register . x logic 1 = enable the uart selected in ldn register. bits [7:1]: reserved 2.1.2.1.2 base address high/low register - read/wri te the v384 provides programmable i/o mapped address f eature. configure the msb/lsb of 16-bit i/o address , for the uart selected in ldn register, in this regi ster. bits [7:0]: msb of uart base address (0x60) the default value of this register is determined by the strapping options. see table 1 ?uart power on configuration? .
xr28v384 23 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo bits [7:0]: lsb of uart base address (0x61) the default value of this register is determined by the strapping options. see table 1 ?uart power on configuration? . 2.1.2.1.3 irq channel select register - read/write the v384 supports different irq channels and modes. the irq modes and irq channel number for each device of v384 should be programmed in their respec tive irq channel selelct register. each device of v 384 can have same/different irq channel. bits [3:0]: select the irq channel the default values of these bits is determined by th e strapping options see table 1 ?uart power on configuration?. they can also be configured via software after powe r on. bit [4]: enable/disable the irq sharing mode x logic 0 = disable the irq sharing mode (default). t he irq channel must be different for each uart for proper behavior. x logic 1 = enable the irq sharing mode. the irq chan nel (bits 3-0) can be different or be the same as t he other uarts. bits [6:5]: irq sharing mode these two bits are effective only when irq sharing m ode is enabled (bit[4] = ?1?). the serirq time slot is specified by bits 3-0. an interrupt will only appea r on the serirq pin during that time slot if mcr[3] = ?1?. x ?00? = the irq sharing mode is active low level (de fault). there will be an active low pulse continuou sly on the serirq pin until the interrupt has been cleared . x ?01? = the irq sharing mode is active low edge. whe n there is an interrupt, there will be a single act ive low pulse on the serirq pin. x ?10? = the irq sharing mode is active high level. t here will be an active high pulse continuously on t he serirq pin until the interrupt has been cleared. x ?11? = reserved. bit [7]: reserved 2.1.2.1.4 enhanced multifunction register - read/wr ite this register enables/disables the rs-485 mode, 9-b it mode, selects clock frequency and delay in the i r mode.
xr28v384 24 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo bits [1:0]: internal clock frequency the v384 provides an option to select among various internal clock frequency, which is used to generat e different baud values. the value of the internal cl ock frequency is dependent on external clock provide d to the clkin pin and setting of clock select register - read/write . table 8 describes various possible internal clock frequencies derived from 24mhz/48mhz external clock. see ?section 1.4.1.1, programmable baud rate genera tor? . bit [2]: ir mode tx delay x logic 0 = tx transmits data immedately when changin g from rx to tx (default). x logic 1 = tx delays 4 character time when changing from rx to tx. bit [3]: ir mode rx delay x logic 0 = rx is enabled immediately after tx is idl e (default). x logic 1 = rx is disabled for 4 character time after tx is idle. bit [4]: enable/disable auto rs-485 half-duplex con trol mode x logic 0 = disable the auto rs-485 half-duplex contr ol mode (default). the rts#/rs485 pin can be controlled by mcr bit-1. x logic 1 = enable the auto rs-485 half-duplex contro l mode. the rts#/rs485 signal polarity is determine d by the bit-5. bit [5]: invert the rts#/rs485 signal polarity for rs-485 half-duplex control mode x logic 0 = rts#/rs485 signal polarity is high for tr ansmission and low for reception (default). x logic 1 = rts#/rs485 signal polarity is inverted (t hat is, low for transmission and high for reception ). bit [6]: auto address detection x logic 0 = all bytes received will be loaded into rx fifo. see ?section 1.4.4, auto rs-485 half-duplex control? . x logic 1 = all bytes received after address byte tha t matches the given address or broadcast address (determined by the 9-bit mode slave address register and 9-bit mode slave address mask register) will be loaded into rx fifo. see ?section 1.4.5.1, auto address detection? . bit [7]: enable/disable the 9-bit mode x logic 0 = disable the 9-bit mode (default). x logic 1 = enable the 9-bit mode (multi-drop mode). in the 9-bit mode, the parity bit becomes the addre ss/data bit. see ?section 1.4.5, normal multidrop (9-bit) mode? . t able 8: i nternal c lock f requency (mh z ) bit s [1:0] e xternal c lock = 24mh z e xternal c lock = 48mh z clksel=0 x 0 clksel=0 x 1 clksel=0 x 0 clksel =0 x 1 00 1.8462 0.9231 3.6923 1.8462 01 18 9 36 18 10 24 12 48 24 11 14 7 28 14
xr28v384 25 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo 2.1.2.1.5 infrared mode control register - read/write the v384 supports ir mode for uart channel a only. i t controls infrared mode by setting this register. see ?section 1.4.6, infrared mode?. bit [0]: ir mode irrxa# invert x logic 0 = irra# idles low. (default) x logic 1 = invert the irrxa# for ir mode, idle at hi gh. bit [1]: ir mode irtxa# invert x logic 0 = irtxa# idles low. (default) x logic 1 = invert the irtxa# for ir mode, idle at hi gh. bit [2]: ir mode half-duplex x logic 0 = enable full duplex function for ir mode. x logic 1 = enable half duplex function for ir mode ( default). bits [4:3]: ir mode enable x ?00? or ?01? = disable the ir function (default val ue is ?00?). x ?10? = enable the ir function, active pulse is 1.6 u s. x ?11? = enable the ir function, active pulse is 3/16 bit time. bits [7:5]: reserved 2.1.2.1.6 9-bit mode slave address register - read/ write this register indicates the slave address in 9-bit mode. this register along with the 9-bit mode slave address mask register will determine the given address and b roadcast address in 9-bit mode. the v384 will respo nd to both the given address and the broadcast address. 2.1.2.1.7 9-bit mode slave address mask register - read/write this register indicates the slave address mask in 9 -bit mode. this register along with the 9-bit mode slave address register will determine the given address an d broadcast address in 9-bit mode. the v384 will re spond to both the given address and the broadcast address . x given address: if bit n of the 9-bit mode slave addr ess mask register is ?0?, then the corresponding bit of given address is ?do not care?. x broadcast address: if bit n of the ored 9-bit mode slave address register and 9-bit mode slave address mask register is ?0?, then this bit n is a ?do not care? bit. the remaining bit which is ?1? is compar ed to the received address. t able 9: e xample r egister e xample 1 e xample 2 e xample 3 e xample 4 9-bit mode slave address register (0xf4) 11110100 000 01111 01010101 11100111 9-bit mode slave address mask register (0xf5) 01010101 10101010 11111111 00001111 given address x1x1x1x0 0x0x1x1x 01010101 xxxx0111 broadcast address 1111x1x1 1x1x1111 11111111 111x1111
xr28v384 26 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo 2.1.2.1.8 fifo mode select register - read/write this register selects fifo depth and receiver trigger levels. bits [1:0]: fifo size for tx/rx x ?00? = fifo size is 16 bytes. x ?01? = fifo size is 32 bytes. x ?10? = fifo size is 64 bytes. x ?11? = fifo size is 128 bytes. bits [3:2]: reserved bits [5:4]: rx trigger level x ?00? = rx trigger level is 1, 4, 8, 14 ( see table 13 ?receive fifo trigger level selection? ). x ?01? = rx trigger level is 2, 8, 16, 28 ( see table 13 ?receive fifo trigger level selection? ). x ?10? = rx trigger level is 4, 16, 32, 56 ( see table 13 ?receive fifo trigger level selection? ). x ?11? = rx trigger level is 8, 32, 64, 112 ( see table 13 ?receive fifo trigger level selection? ). note: for bits[5:4]= ?01?,?10? and ?11? make sure correct fifo size is programmed in bits[1:0]. bit [6]: reserved bit [7]: tx holding register (thr) empty delay x logic 0 = no delay for thr empty interrupt (default ). x logic 1 = delay 1 transmission clock for thr empty interrupt. 2.1.2.2 watchdog timer registers (ldn = 0x08) 2.1.2.2.1 wdt enable register - read/write bit [0]: wdt enable/disable x logic 0 = disable the watchdog timer. x logic 1 = enable the watchdog timer. after power on or reset, if the pin dtrc#/ps_wdt is sampled high, this bit will be set to ?1?. otherwi se, this bit will be set to ?0?. see table 1 ?uart power on configuration? . bits [7:1]: reserved 2.1.2.2.2 wdt base address high/low register - read /write this register indicates the msb/lsb of watchdog tim er base address. bits [7:0]: the msb of watchdog timer base address (0x60). after power on or reset, if the pin dtrc#/ps_wdt is sampled high, this byte will be set to 0x04. other wise, this bit will be set to 0x00. see table 1 ?uart power on configuration? . bits [7:0]: the lsb of watchdog timer base address (0x61) . after power on or reset, if the pin dtrc#/ps_wdt is sampled high, this byte will be set to 0x42. other wise, this byte will be set to 0x0. see table 1 ?uart power on configuration? . 2.1.2.2.3 wdt irq channel select register - read/wr ite this register enables / disables an interrupt reque st output from the watchdog timer.
xr28v384 27 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo bits [3:0]: select the irq channel for watchdog tim er after power on or reset, if the pin dtrc#/ps_wdt is sampled high, this byte will be set to 0x00. other wise, this byte will be set to 0x0. see table 1 ?uart power on configuration? . bit [4]: enable/disable the watchdog timer irq x logic 0 = disable the watchdog timer irq (default). x logic 1 = enable the watchdog timer irq. bits [7:5]: reserved 2.1.2.2.4 wdt timer status and control register - r ead/write this register sets timer status and control timer e vents. bit [0]: time out events x logic 0 = no time out occurred (default). x logic 1 = time out occurred. write ?1? to this bit will clear the status. bits [2:1]: wdt interval x ?00? = timer unit is 10 ms. x ?01? = timer unit is 1 second. x ?10? = timer unit is 1 minute. x ?11? = reserved. bits [7:3]: reserved 2.1.2.2.5 wdt count register - read/write this register programs the count value for watchdog timer. bits [7:0]: sets count value for watchdog timer writing a non-zero value to this register once wil l disable the timer and writing the same value aga in will enable the timer. after power on or reset, if the p in dtrc#/ps_wdt is sampled high, this byte will be set to 0x0a. otherwise, this byte will be set to 0x00. see table 1 ?uart power on configuration? .
xr28v384 28 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo 2.2 uart internal registers the uart register set for the v384 is shown in table 10 and table 11 . t able 10: uart i nternal r egisters o ffset a ddresses r egister r eset s tate c omments 16c550 c ompatible r egisters 0x0 dll - divisor lsb register 0x01 lcr[7] = 1 0x1 dlm - divisor msb register 0x00 0x0 rhr - receive holding register thr - transmit holding register 0xxx 0xxx lcr[7] = 0 0x1 ier - interrupt enable register 0x00 0x2 isr - interrupt status register fcr - fifo control register 0x01 0x00 0x3 lcr - line control register 0x00 0x4 mcr - modem control register 0x00 0x5 lsr - line status register 0x60 0x6 msr - modem status register bits 3:0 = 0 bts 7-4 = logic levels of the inputs inverted 0x7 spr - scratch pad register 0x00
xr28v384 29 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo 2.2.1 uart internal register descriptions 2.2.1.1 receive holding register (rhr) - read- only see ?receiver? on page 12. 2.2.1.2 transmit holding register (thr) - write-only see ?transmitter? on page 11. 2.2.1.3 interrupt enable register (ier) - read/write the interrupt enable register (ier) masks the inter rupts from receive data ready, transmit empty, line status and modem status registers. these interrupts are re ported in the interrupt status register (isr). t able 11: uart i nternal r egister o ffset a ddress r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment 16c550 compatible registers 0x0 rhr rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 0 0x0 thr wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0x1 ier rd/wr 0 0 0 0 modem stat. int. enable rx line stat. int. enable tx empty int enable rx data int. enable 0x2 isr rd fifos enabled fifos enabled 0 0 int source bit-3 int source bit-2 int source bit-1 int source bit-0 0x2 fcr wr rx fifo trigger rx fifo trigger 0 0 0 tx fifo reset rx fifo reset fifos enable 0x3 lcr rd/wr divisor enable set tx break set parity even parity parity enable stop bits word length bit-1 word length bit-0 0x4 mcr rd/wr 0 0 0 internal lopback enable enable interrupts/ op2# op1# rts# output control dtr# output control 0x5 lsr rd rx fifo global error thr & tsr empty thr empty rx break rx fram- ing error rx parity error rx over- run error rx data ready 0x6 msr rd cd# input ri# input dsr# input cts# input delta cd# delta ri# delta dsr# delta cts# 0x7 spr rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 baud rate generator divisor 0x0 dll rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 1 0x1 dlm rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
xr28v384 30 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo 2.2.1.3.1 ier versus receive fifo interrupt mode ope ration when the receive fifo (fcr bit-0 = 1) and receive i nterrupts (ier bit-0 = 1) are enabled, the rhr inte rrupts (see isr bits 2 and 3) status will reflect the follo wing: a. the receive data available interrupts are issued to the host when the fifo has reached the programmed trigger level. it will be cleared when the fifo dro ps below the programmed trigger level. b. fifo level will be reflected in the isr register wh en the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared when t he fifo drops below the trigger level. c. the receive data ready bit (lsr bit-0) is set as so on as a character is transferred from the shift reg ister to the receive fifo. it is reset when the fifo is empt y. 2.2.1.3.2 ier versus receive/transmit fifo polled mo de operation when fcr bit-0 equals a logic 1 for fifo enable; re setting ier bits 0-3 enables the xr28v384 in the fif o polled mode of operation. since the receiver and tr ansmitter have separate bits in the lsr either or bo th can be used in the polled mode by selecting respective transmit or receive control bit(s). a. lsr bit-0 indicates there is data in rhr or rx fifo. b. lsr bit-1 indicates an overrun error has occurred an d that data in the fifo may not be valid. c. lsr bit 2-4 provides the type of receive data error s encountered for the data byte in rhr, if any. d. lsr bit-5 indicates thr is empty. e. lsr bit-6 indicates when both the transmit fifo and tsr are empty. f. lsr bit-7 indicates a data error in at least one ch aracter in the rx fifo. ier[0]: rhr interrupt enable the receive data ready interrupt will be issued whe n rhr has a data character in the non-fifo mode or w hen the receive fifo has reached the programmed trigger level in the fifo mode. x logic 0 = disable the receive data ready interrupt (default). x logic 1 = enable the receiver data ready interrupt. ier[1]: thr interrupt enable this bit enables the transmit ready interrupt which is issued whenever the thr becomes empty. if the t hr is empty when this bit is enabled, an interrupt will b e generated. x logic 0 = disable transmit ready interrupt (default ). x logic 1 = enable transmit ready interrupt. ier[2]: receive line status interrupt enable if any of the lsr register bits 1, 2, 3 or 4 is a lo gic 1, it will generate an interrupt to inform the host controller about the error status of the current data byte in fifo. lsr bit-1 generates an interrupt immediately when an overrun occurs. lsr bits 2-4 generate an interrupt wh en the character in the rhr has an error. x logic 0 = disable the receiver line status interrup t (default). x logic 1 = enable the receiver line status interrupt . ier[3]: modem status interrupt enable x logic 0 = disable the modem status register interru pt (default). x logic 1 = enable the modem status register interrup t. ier[7:4]: reserved
xr28v384 31 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo 2.2.1.4 interrupt status register (isr) - read-only the uart provides multiple levels of prioritized in terrupts to minimize external software interaction. the interrupt status register (isr) provides the user wit h six interrupt status bits. performing a read cycle on the isr will give the user the current highest pending interrupt level to be serviced, others are queued u p to be serviced next. no other interrupts are acknowledged u ntil the pending interrupt is serviced. the interru pt source table, table 12 , shows the data values (bit 0-3) for the interrupt priority levels and the interrupt sources associated with each of these interrupt levels. 2.2.1.4.1 interrupt generation: x lsr is by any of the lsr bits 1, 2, 3 and 4. x rxrdy data ready is by rx trigger level. x rxrdy data time-out is by a 4-char plus 12 bits del ay timer. x txrdy is by tx fifo empty. x msr is by any of the msr bits 0, 1, 2 and 3. 2.2.1.4.2 interrupt clearing: x lsr interrupt is cleared by a read to the lsr regis ter. x rxrdy interrupt is cleared by reading data until fi fo falls below the trigger level. x rxrdy time-out interrupt is cleared by reading rhr. x txrdy interrupt is cleared by a read to the isr reg ister or writing to thr. x msr interrupt is cleared by a read to the msr regis ter. ] isr[0]: interrupt status x logic 0 = an interrupt is pending and the isr conte nts may be used as a pointer to the appropriate int errupt service routine. x logic 1 = no interrupt pending (default condition). isr[3:1]: interrupt status these bits indicate the source for a pending interru pt at interrupt priority levels (see interrupt sour ce table 12 ). isr[4]: reserved isr[5]: reserved t able 12: i nterrupt s ource and p riority l evel p riority isr r egister s tatus b its s ource of interrupt l evel b it -3 b it -2 b it -1 b it -0 1 0 1 1 0 lsr (receiver line status register) 2 1 1 0 0 rxrdy (receive data time-out) 3 0 1 0 0 rxrdy (received data ready) 4 0 0 1 0 txrdy (transmit ready) 5 0 0 0 0 msr (modem status register) - 0 0 0 1 none (default)
xr28v384 32 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo isr[7:6]: fifo enable status these bits are set to a logic 0 when the fifos are d isabled. they are set to a logic 1 when the fifos a re enabled. 2.2.1.5 fifo control register (fcr) - write-only this register is used to enable the fifos, clear the fifos, and set the receive fifo trigger levels. th e fifo mode is defined as follows: fcr[0]: tx and rx fifo enable x logic 0 = disable the transmit and receive fifo (de fault). x logic 1 = enable the transmit and receive fifos. th is bit must be set to logic 1 when other fcr bits ar e written or they will not be programmed. see fifo mode select register - read/write bit [1:0] for fifo size selection. fcr[1]: rx fifo reset this bit is only active when fcr bit-0 is a ?1?. x logic 0 = no receive fifo reset (default). x logic 1 = reset the receive fifo pointers and fifo l evel counter logic (the receive shift register is n ot cleared or altered). this bit will return to a logi c 0 after resetting the fifo. fcr[2]: tx fifo reset this bit is only active when fcr bit-0 is a ?1?. x logic 0 = no transmit fifo reset (default). x logic 1 = reset the transmit fifo pointers and fifo level counter logic (the transmit shift register i s not cleared or altered). this bit will return to a logi c 0 after resetting the fifo. fcr[5:3]: reserved
xr28v384 33 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo fcr[7:6]: receive fifo trigger select (logic 0 = default, rx trigger level =1). these 2 bits are used to set the trigger level for t he receive fifo. the uart will issue a receive inte rrupt when the number of the characters in the fifo crosses th e trigger level. table 13 shows the complete selections. 2.2.1.6 line control register (lcr) - read/write the line control register is used to specify the asyn chronous data communication format. the word or character length, the number of stop bits, and the p arity are selected by writing the appropriate bits i n this register. lcr[1:0]: tx and rx word length select these two bits specify the word length to be transmi tted or received. t able 13: r eceive fifo t rigger l evel s election fifo m ode s elect r egister fcr b it -7 fcr b it -6 r eceive t rigger l evel b it -5 b it -4 0 0 00 1 1 01 0 1 1 (default) 48 14 0 1 00 1 1 01 0 1 28 16 28 1 0 00 1 1 01 0 1 4 16 32 56 1 1 00 1 1 01 0 1 8 32 64 112 bit-1 bit-0 w ord length 0 0 5 (default) 0 1 6 1 0 7 1 1 8
xr28v384 34 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo lcr[2]: tx and rx stop-bit length select the length of stop bit is specified by this bit in conjunction with the programmed word length. lcr[3]: tx and rx parity select parity or no parity can be selected via this bit. t he parity bit is a simple way used in communication s for data integrity check. see table 14 for parity selection summary below. x logic 0 = no parity. x logic 1 = a parity bit is generated during the tran smission while the receiver checks for parity error of the data character received. lcr[4]: tx and rx parity select if the parity bit is enabled with lcr bit-3 set to a logic 1, lcr bit-4 selects the even or odd parity format. x logic 0 = odd parity is generated by forcing an odd number of logic 1?s in the transmitted character. the receiver must be programmed to check the same forma t (default). x logic 1 = even parity is generated by forcing an ev en number of logic 1?s in the transmitted character . the receiver must be programmed to check the same forma t. lcr[5]: tx and rx parity select if the parity bit is enabled, lcr bit-5 selects the forced parity format. x lcr bit-5 = logic 0, parity is not forced (default) . x lcr bit-5 = logic 1 and lcr bit-4 = logic 0, parity bit is forced to high for the transmit and receive data. x lcr bit-5 = logic 1 and lcr bit-4 = logic 1, parity bit is forced to low for the transmit and receive data. lcr[6]: transmit break enable when enabled, the break control bit causes a break co ndition to be transmitted (the tx output is forced t o a ?space?, logic 0, state). this condition remains, u ntil disabled by setting lcr bit-6 to a logic 0. x logic 0 = no tx break condition. (default). x logic 1 = forces the transmitter output (tx) to a ?sp ace?, logic 0, for alerting the remote receiver of a line break condition. bit-2 w ord length s top bit length (b it time ( s )) 0 5,6,7,8 1 (default) 1 5 1-1/2 1 6,7,8 2 t able 14: p arity selection lcr b it -5 lcr b it -4 lcr b it -3 p arity selection x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 force parity to mark, high 1 1 1 forced parity to space, low
xr28v384 35 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo lcr[7]: baud rate divisors enable baud rate generator divisor (dll/dlm) enable. x logic 0 = data registers are selected (default). x logic 1 = divisor latch registers are selected. 2.2.1.7 modem control register (mcr) or general purp ose outputs control - read/write the mcr register is used for controlling the serial /modem interface signals or general purpose inputs/ outputs. mcr[0]: dtr# output the dtr# pin is a modem control output. if the mode m interface is not used, this output may be used as a general purpose output. x logic 0 = force dtr# output high (default). x logic 1 = force dtr# output low. mcr[1]: rts# output the rts# pin is a modem control output. if the mode m interface is not used, this output may be used as a general purpose output. x logic 0 = force rts# output high (default). x logic 1 = force rts# output low. mcr[2]: reserved op1# is not available as an output pin on the v384. but it is available for use during internal loopba ck mode. in the loopback mode, this bit is used to write the state of the modem ri# interface signal. mcr[3]: enable interrupts on serirq / op2# enable or disable interrupt outputs. x logic 0 = interrupts will not appear on serirq pin. x logic 1 = if enabled in ier, interrupting condition will appear on serirq pin. in internal loopback mode (mcr[4] = ?1?), this bit controls the op2# signal. see ?section 1.4.7, internal loopback?. mcr[4]: internal loopback enable x logic 0 = disable loopback mode (default). x logic 1 = enable local loopback mode, see loopback section and figure 8 . mcr[7:5]: reserved 2.2.1.8 line status register (lsr) - read-only the lsr provides the status of data transfers betwee n the uart and the host. if ier bit-2 is enabled, l sr bit- 1 will generate an interrupt immediately and lsr bi ts 2-4 will generate an interrupt when a character with an error is in the rhr. lsr[0]: receive data ready indicator x logic 0 = no data in receive holding register or fi fo (default). x logic 1 = data has been received and is saved in th e receive holding register or fifo.
xr28v384 36 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo lsr[1]: receiver overrun flag x logic 0 = no overrun error (default). x logic 1 = overrun error. a data overrun error condi tion occurred in the receive shift register. this h appens when additional data arrives while the fifo is full . in this case the previous data in the receive shi ft register is overwritten. note that under this condition the data byte in the receive shift register is not tran sferred into the fifo, therefore the data in the fifo is not cor rupted by the error. lsr[2]: receive data parity error tag x logic 0 = no parity error (default). x logic 1 = parity error. the receive character in rh r does not have correct parity information and is s uspect. this error is associated with the character availab le for reading in rhr. lsr[3]: receive data framing error tag x logic 0 = no framing error (default). x logic 1 = framing error. the receive character did not have a valid stop bit(s). this error is associa ted with the character available for reading in rhr. lsr[4]: receive break tag x logic 0 = no break condition (default). x logic 1 = the receiver received a break signal (rx was low for at least one character frame time). in the fifo mode, only one break character is loaded into t he fifo. the break indication remains until the rx input returns to the idle condition, ?mark? or high . lsr[5]: transmit holding register empty flag this bit is the transmit holding register empty ind icator. the thr bit is set to a logic 1 when the la st data byte is transferred from the transmit holding register t o the transmit shift register. the bit is reset to logic 0 concurrently with the data loading to the transmit holding register by the host. in the fifo mode this bit is set when the transmit fifo is empty, it is cleared when the transmit fifo contains at least 1 byte. lsr[6]: thr and tsr empty flag this bit is set to a logic 1 whenever the transmitt er goes idle. it is set to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode thi s bit is set to a logic 1 whenever the transmit fif o and transmit shift register are both empty. lsr[7]: receive fifo data error flag x logic 0 = no fifo error (default). x logic 1 = a global indicator for the sum of all err or bits in the rx fifo. at least one parity error, fr aming error or break indication is in the fifo data. this bit c lears when there is no more error(s) in any of the b ytes in the rx fifo. 2.2.1.9 modem status register (msr) - read-only the msr provides the current state of the modem inte rface input signals. lower four bits of this regist er are used to indicate the modified information. these bi ts are set to a logic 1 whenever a signal from the m odem changes state. these bits may be used for general p urpose inputs when they are not used with modem signals. msr[0]: delta cts# input flag x logic 0 = no change on cts# input (default). x logic 1 = the cts# input has changed state since th e last time it was monitored. a modem status interr upt will be generated if msr interrupt is enabled (ier bit-3).
xr28v384 37 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo msr[1]: delta dsr# input flag x logic 0 = no change on dsr# input (default). x logic 1 = the dsr# input has changed state since the last time it was monitored. a modem status interru pt will be generated if msr interrupt is enabled (ier bit-3). msr[2]: delta ri# input flag x logic 0 = no change on ri# input (default). x logic 1 = the ri# input has changed from low to hig h, ending of the ringing signal. a modem status interrupt will be generated if msr interrupt is ena bled (ier bit-3). msr[3]: delta cd# input flag x logic 0 = no change on cd# input (default). x logic 1 = indicates that the cd# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3). msr[4]: cts input status normally msr bit-4 bit is the compliment of the cts # input. however in the loopback mode, this bit is equivalent to the rts# bit in the mcr register. the cts# input may be used as a general purpose input when the modem interface is not used. msr[5]: dsr input status normally this bit is the complement of the dsr# inp ut. in the loopback mode, this bit is equivalent to the dtr# bit in the mcr register. the dsr# input may be used as a general purpose input when the modem interface is not used. msr[6]: ri input status normally this bit is the complement of the ri# inpu t. in the loopback mode this bit is equivalent to bi t-2 in the mcr register. the ri# input may be used as a general purpose input when the modem interface is not used. msr[7]: cd input status normally this bit is the complement of the cd# inpu t. in the loopback mode this bit is equivalent to b it-3 in the mcr register. the cd# input may be used as a general purpose input when the modem interface is not used. 2.2.1.10 scratch pad register (spr) - read/write this is a 8-bit general purpose register for the us er to store temporary data. 2.2.1.11 baud rate generator registers (dll and dlm) - read/write these registers make-up the value of the baud rate divisor. the concatenation of the contents of dlm an d dll gives the 16-bit divisor value.
xr28v384 38 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo absolute maximum ratings power supply range 4 volts voltage at any pin 6 v operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c package dissipation 500 mw electrical characteristics dc electrical characteristics u nless otherwise noted : ta = -40 o to +85 o c, v cc is 3.3v 10% s ymbol p arameter l imits 3.3v m in m ax u nits c onditions v il input low voltage -0.5 0.8 v v ih input high voltage 2.0 5.5 v v ol output low voltage 0.4 v i ol = 16 ma serirq, lad[3:0] v oh output high voltage 2.4 v i oh = -16 ma serirq, lad[3:0] v ol output low voltage 0.4 v i ol = 12 ma wdtout# v ol output low voltage 0.4 v i ol = 8 ma all other ouputs v oh output high voltage 2.4 v i oh = -8 ma all other ouputs i il input low leakage current -10 ua pins without internal pull-up resistor. i ih input high leakage current 10 ua i il input low leakage current -110 ua pins with internal p ull- up resistor. i ih input high leakage current 60 ua c in input pin capacitance 10 pf i cc power supply current 17 ma r int internal pull-up resistor 37 110 k ohm
xr28v384 39 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo ac electrical characteristics u nless otherwise noted : ta = -40 o to +85 o c, v cc is 3.3v 10% s ymbol p arameter l imits 3.3v 10% m in m ax u nit n otes - external clock 48 mhz clkin f igure 11. lpc t iming d iagram 2.0 v p-t-p (minimum) 2.4 v 0.4 v lclk bused signal output delay tri-state output tvalid (2-11 nsec) ton (2 nsec min) toff (28 nsec max) 11 nsec (min) 4 nsec (max) 4 nsec (max) 11 nsec (min) tsetup (7 nsec min) thold (0 nsec) bused signal input lpc_clk inputs valid
xr28v384 40 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo package ecn 1344-16 11/01/2013
xr28v384 41 rev. 1.0.0 3.3v quad lpc uart with 128-byte fifo n otes : 1. tqfp48 theta ja = 64.1 deg. c/w, theta jc = 6.5 deg. c / w. all values are typical. 2. tqfp100 dimensions do not apply to this device. ecn 1344-16 11/01/2013
42 notice exar corporation reserves the right to make changes to the products contained in this publication in or der to improve design, performance or reliability. exar co rporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representat ion that the circuits are free of patent infringement. charts and schedules contained here in are only for illustr ation purposes and may vary depending upon a user?s specif ic application. while the information in this publi cation has been carefully checked; no responsibility, howe ver, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where t he failure or malfunction of the product can reasonably be expected to cause failure of the life support s ystem or to significantly affect its safety or effectiveness . products are not authorized for use in such applic ations unless exar corporation receives, in writing, assurances t o its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks ; (c) potential liability of exar corporation is ad equately protected under the circumstances. copyright 2013 exar corporation datasheet november 2013. reproduction, in part or whole, without the prior w ritten consent of exar corporation is prohibited. xr28v384 3.3v quad lpc uart with 128-byte fifo rev. 1.0.0 revision history d ate r evision d escription november 2013 1.0.0 released datasheet ecn: 1349-03

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